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EquivSVA: A Formally Verified Dataset of Behavioral Assertions Across Equivalent RTL Implementations

arXiv · AI, language, vision and robotics · article · Sep 22, 2026 · UTC

Large language models are increasingly used to generate SystemVerilog Assertions from natural-language specifica- tions and register-transfer-level designs. Existing datasets and benchmarks support important goals such as large- scale training, formal evaluation, specification-to-assertion generation, and mutation-based testing. A complemen- tary need is to study whether a generated assertion cap- tures externally observable behavior or depends on inci- dental details of one RTL implementation. We present EquivSVA, a formally verified dataset organized around behavior families. Each family con

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